As semiconductor technology continues to scale, energy efficiency is becoming a key design concern for computer systems. Processors often use multiple power modes to exploit the power-performance tradeoff in order to improve energy efficiency. Many processors support high-performance and low-power modes of operation. While operating in a high-performance mode, the processor uses normal supply voltage and runs at a high frequency to achieve the best performance. However, while operating in low-power mode(s), the processor may operate at a lower frequency and may use lower supply voltages (500 to 600 mv) to conserve energy. Since energy efficiency is becoming a primary design goal for modern processors, current architectures support many features to reduce power consumption.
Reducing supply voltage may be used to reduce power consumption. However, as supply voltage decreases, manufacturing induced parameter variations increase in severity, which may cause circuits to fail. These variations restrict voltage scaling to a minimum value (Vmin), which is the minimum supply voltage for a die to operate reliably. Failures in memory cells typically determine the Vmin for a processor as a whole. Reducing Vmin in the context of memory failures may be an important factor for enabling ultra-tow power mode of operation.